The present invention relates to an electro-static discharge (ESD) protection circuit, and more particularly to an ESD protection circuit capable of protecting a gate insulating layer of a NMOS transistor constituting an internal circuit of a semiconductor.
In general, an ESD protection circuit represents a circuit formed between an internal circuit of a semiconductor and a pad connected to an external input/output pin in order to prevent the destruction or deterioration of products due to an ESD when designing the semiconductor device.
If an electrically charged human body or machine makes contact with a semiconductor circuit, the ESD accumulated in the human body or the machine is discharged inside the semiconductor circuit through an external pin of the semiconductor circuit via an input/output pad. Accordingly, excessive current having high energy due to the discharge may inflict fatal damage on an internal circuit of the semiconductor.
Most semiconductor circuits include an ESD protection circuit between the input/output pad and the internal circuit of the semiconductor so as to prevent the semiconductor circuit from being damaged by an ESD.
In the meantime, with the development of semiconductor technology, the gate insulating layer of an NMOS transistor constituting an internal circuit of the semiconductor becomes thinner. If the gate insulating layer becomes thinner, a lower destructive voltage can cause harm to the gate insulating layer. Therefore, the internal circuits of a semiconductor device should be protected from being easily damaged by an ESD.
FIG. 1 is a circuit diagram illustrating the conventional ESD protection circuit, which shows an electrostatic discharge circuit 100, an input buffer 120, and an internal circuit 140.
Since the gate of an NMOS transistor N1 included in the input buffer 120 is directly connected to the input/output pad 102, it is very susceptible to an excessive ESD voltage applied through the input/output pad 102.
To solve this problem, an NMOS transistor N2 for electrostatic protection is installed between the input/output pad 102 and the input buffer 120. When the gate voltage of the NMOS transistor N1 in the input buffer 120 excessively increases duo to an ESD, the NMOS transistor N2 is turned on for electrostatic protection, thereby preventing damage occurring to the gate insulating layer of the NMOS transistor N1 in the input buffer 120.
However, since the gate of a conventional NMOS transistor N2 used for electrostatic protection is connected to the ground voltage supply pad (VSS), the ESD onset voltage capable of discharging the ESD becomes very high. That is, when the voltage between the drain and the source of the NMOS transistor N2 for electrostatic protection, at which the NMOS transistor N2 starts ESD discharge operation, is higher than the destructive voltage for the gate insulating layer of the NMOS transistor N1 in the input buffer 120, the gate insulating layer of the NMOS transistor N1 in the input buffer 120 is broken before the NMOS transistor N2 for the electrostatic protection operates.